In high speed digital data processing systems data masking circuits find application in field extraction, bit checking and similar operations. The masking circuits generate a selectable pattern of ones and zeroes which are combined in AND circuit networks with data words to selectively delete or mask portions, fields, or bits thereof. As such, masking circuits may be used to read or write bits into or out of a selected portion of a register or memory location.
The broad concept of masking is known in the prior art as demonstrated by the apparatus disclosed in U.S. Pat. No. 3,343,139 issued Sept. 19, 1967 to W. Ulrich and in U.S. Pat. No. 3,482,216 issued Dec. 2, 1969 to E. Geissler. In the prior art, masking circuits have been developed and designed to meet specific parameter requirements of particular computing machines. Thus, prior art masking circuits have limited applicability beyond their specifically designed tasks.
It is therefore an object of the present invention to provide a masking circuit having universal applicability to a wide variety of masking tasks.
It is a further object of the present invention to provide a masking circuit modularly adaptable to a wide range of masking tasks.
It is still a further object of the present invention to provide a high speed modular mask generator circuit suitable for small, medium and large scale integration processes.